====== CPUInfo 1.0-Prerelease ======

The idea behind [[en:projects:cpuinfo|cpuinfo]] was to gather any useful information from new processors we were receiving at Mandriva. By useful information, I mean for me at least, i.e. caches hierarchy, multicore and hyperthreading configurations, processor name generation matching the AMD revision guides, new processor capabilities (e.g. VMX, SVM, SSSE3). Then, once the specs go public, I usually send patches to Dave Jones for [[http://www.codemonkey.org.uk/|x86info]], although sometimes in crippled form. ;-)

The initial workplace was derived from the UAE-JIT processor detection code. I then decided to rewrite it in a cleaner way, with a focus of being extensible and reusable from other programs: (i) build it from a common API/library, (ii) use it through appropriate bindings where needed. cpuinfo was born! And finally, other architectures were added to cover x86, x86_64, ia64, ppc, ppc64, mips. Bindings are currently missing though.

I don't know if people will use it, but at least it was a nice thing to play with, i.e. read a lot of processor documentation! Note this a **secondary**/toy project. This means it's not something to be actively maintained but I'd rather accept patches. I will soon no longer be able to match new processors anyway ([[en:blog:2007:04:01:introduction|see here for a plan and reasons]]). There is a ''TODO'' file available in the sources distribution for interested developers.

Note: if you believe ''cpuinfo'' reports incorrect information, please send relevant data and the output of:
<code>
cpuinfo --debug
</code>

People like examples, here are a few outputs from various systems:

  * My good-old Mandriva Linux 2005LE system
<code>
Processor Information
  Model: AMD Athlon 64 3200+, 1.99 GHz
  Package: Socket 939, 1 Core

Processor Caches
  L1 code cache, 64 KB
  L1 data cache, 64 KB
  L2 unified cache, 512 KB

Processor Features
  64bit      64-bit capable
  simd       SIMD capable
  [x86]      -- x86-specific features --
  cmov       Conditional Moves
  mmx        MMX Technology
  sse        SSE Technology
  sse2       SSE2 Technology
  lm         Long Mode (64-bit capable)
  lahf_lm    LAHF/SAHF Supported in 64-bit mode
</code>

  * The newer MacBook...
<code>
Processor Information
  Model: Intel Core 2 T7200, 2.00 GHz
  Package: 2 Cores

Processor Caches
  L1 code cache, 32 KB
  L1 data cache, 32 KB
  L2 unified cache, 4 MB

Processor Features
  64bit      64-bit capable
  simd       SIMD capable
  [x86]      -- x86-specific features --
  cmov       Conditional Moves
  mmx        MMX Technology
  sse        SSE Technology
  sse2       SSE2 Technology
  pni        SSE3 Technology (Prescott New Instructions)
  mni        SSSE3 Technology (Merom New Instructions)
  vmx        Intel Virtualisation Technology (VT)
  lm         Long Mode (64-bit capable)
  lahf_lm    LAHF/SAHF Supported in 64-bit mode
</code>

  * ... that replaces the aging PowerBook G4
<code>
Processor Information
  Model: Motorola PowerPC 7410, 400 MHz
  Package: 1 Core

Processor Caches
  L1 code cache, 32 KB
  L1 data cache, 32 KB
  L2 unified cache, 1 MB

Processor Features
  simd       SIMD capable
  [ppc]      -- ppc-specific features --
  vmx        Vector instruction set (AltiVec, VMX)
</code>

  * One of the Itanium platforms available at [[http://www.testdrive.hp.com/|HP TestDrive]]
<code>
Processor Information
  Model: Intel Itanium 2 'McKinley', 1.40 GHz
  Package: 1 Core

Processor Caches
  L1 code cache, 16 KB
  L1 data cache, 16 KB
  L2 unified cache, 256 KB
  L3 unified cache, 1.50 MB

Processor Features
  [ia64]     -- ia64-specific features --
  lb         Long branch (brl) instruction available
</code>

  * A 16-way MIPS system available at SGI:
<code>
Processor Information
  Model: MIPS Technologies R12000, 400 MHz
  Package: 1 Core

Processor Caches
  L1 code cache, 32 KB
  L1 data cache, 32 KB
  L2 unified cache, 8 MB

Processor Features
  [mips]     -- mips-specific features --
</code>

{{tag>projects cpuinfo}}